// +FHDR============================================================================/
// Author       : 
// Creat Time   : 
// File Name    : ddr4_tb.sv
// Module Ver   : Vx.x
//
//
// All Rights Reserved
//
// ---------------------------------------------------------------------------------/
//
// Modification History:
// V1.0         initial
//
// -FHDR============================================================================/
// 
// ddr4_tb
//    |---
// 
`timescale 1ns/1ps

module ddr4_tb #
(
    parameter                           U_DLY = 1                     // 
);

reg                                     clk_40m                     ; 
reg                                     rst_sys_n                   ; 

reg                                     clk_ddr0_p                  ; 
wire                                    clk_ddr0_n                  ; 
reg                                     clk_ddr1_p                  ; 
wire                                    clk_ddr1_n                  ; 

reg                                     axi4_s0_clk                 ; 
reg                                     axi4_s0_rst_n               ; 

wire                              [3:0] axi4_s0_awid                ; 
wire                             [31:0] axi4_s0_awaddr              ; 
wire                              [7:0] axi4_s0_awlen               ; 
wire                              [1:0] axi4_s0_awburst             ; 
wire                              [2:0] axi4_s0_awsize              ; 
wire                                    axi4_s0_awready             ; 
wire                                    axi4_s0_awvalid             ; 

wire                            [127:0] axi4_s0_wdata               ; 
wire                             [15:0] axi4_s0_wstrb               ; 
wire                                    axi4_s0_wlast               ; 
wire                                    axi4_s0_wready              ; 
wire                                    axi4_s0_wvalid              ; 

wire                              [3:0] axi4_s0_bid                 ; 
wire                              [1:0] axi4_s0_bresp               ; 
wire                                    axi4_s0_bready              ; 
wire                                    axi4_s0_bvalid              ; 

wire                              [3:0] axi4_s0_arid                ; 
wire                             [31:0] axi4_s0_araddr              ; 
wire                              [7:0] axi4_s0_arlen               ; 
wire                              [1:0] axi4_s0_arburst             ; 
wire                              [2:0] axi4_s0_arsize              ; 
wire                                    axi4_s0_arready             ; 
wire                                    axi4_s0_arvalid             ; 

wire                              [3:0] axi4_s0_rid                 ; 
wire                            [127:0] axi4_s0_rdata               ; 
wire                              [1:0] axi4_s0_rresp               ; 
wire                                    axi4_s0_rlast               ; 
wire                                    axi4_s0_rready              ; 
wire                                    axi4_s0_rvalid              ; 


wire                             [16:0] ddr4_ch0_addr               ; 
wire                              [1:0] ddr4_ch0_ba                 ; 
wire                                    ddr4_ch0_bg                 ; 
wire                                    ddr4_ch0_cke                ; 
wire                                    ddr4_ch0_ck_p               ; 
wire                                    ddr4_ch0_ck_n               ; 
wire                                    ddr4_ch0_reset_n            ; 
wire                                    ddr4_ch0_cs_n               ; 
wire                             [63:0] ddr4_ch0_dq                 ; 
wire                              [7:0] ddr4_ch0_dqs_p              ; 
wire                              [7:0] ddr4_ch0_dqs_n              ; 
wire                              [7:0] ddr4_ch0_dm_dbi_n           ; 
wire                                    ddr4_ch0_odt                ; 
wire                                    ddr4_ch0_act_n              ; 
wire                                    ddr4_ch0_ten                ; 
wire                                    ddr4_ch0_par                ; 

wire                             [16:0] ddr4_ch1_addr               ; 
wire                              [1:0] ddr4_ch1_ba                 ; 
wire                                    ddr4_ch1_bg                 ; 
wire                                    ddr4_ch1_cke                ; 
wire                                    ddr4_ch1_ck_p               ; 
wire                                    ddr4_ch1_ck_n               ; 
wire                                    ddr4_ch1_reset_n            ; 
wire                                    ddr4_ch1_cs_n               ; 
wire                             [63:0] ddr4_ch1_dq                 ; 
wire                              [7:0] ddr4_ch1_dqs_p              ; 
wire                              [7:0] ddr4_ch1_dqs_n              ; 
wire                              [7:0] ddr4_ch1_dm_dbi_n           ; 
wire                                    ddr4_ch1_odt                ; 
wire                                    ddr4_ch1_act_n              ; 
wire                                    ddr4_ch1_ten                ; 
wire                                    ddr4_ch1_par                ; 

genvar                                  i                           ;
integer                                 m                           ;


reg                       [128*128-1:0] axi_wrmem                   ; 



initial begin

    clk_40m = 0;
    rst_sys_n = 0;
    clk_ddr0_p = 0;
    clk_ddr1_p = 0;
    axi4_s0_clk = 0;
    axi4_s0_rst_n = 0;

    #1000;
    rst_sys_n = 'd1;
    #2000; 
    axi4_s0_rst_n = 'd1;

    if(u0_sim_examp_axi_ddr4_top.rst_ddr1)
        @(~u0_sim_examp_axi_ddr4_top.rst_ddr1);
    #2000;
    for(m=0;m<16*256;m=m+1) begin
        axi_wrmem[m*32+:32] = m[31:0];
    end
    u_axi4_mdl.axi4_write(0,1,1,32'h40000000,64,4);
    u_axi4_mdl.axi4_write(0,1,1,32'h40001000,15,4);
    u_axi4_mdl.axi4_write(0,1,1,32'h80002000,64,4);
    u_axi4_mdl.axi4_write(0,1,1,32'h80003000,15,4);
    u_axi4_mdl.axi4_write(0,1,1,32'hc0000000,16,4);
    u_axi4_mdl.axi4_write(0,1,1,32'hc0000200,15,4);
    u_axi4_mdl.axi4_read(0,1,1,32'h40000000,66,4);
    u_axi4_mdl.axi4_read(0,1,1,32'h40001000,15,4);
    u_axi4_mdl.axi4_read(0,1,1,32'h80002000,66,4);
    u_axi4_mdl.axi4_read(0,1,1,32'h80003000,15,4);
    u_axi4_mdl.axi4_read(0,1,1,32'hc0000000,18,4);
    u_axi4_mdl.axi4_read(0,1,1,32'hc0000200,15,4);
end

always #12.5  clk_40m = ~clk_40m;
always #3.125 clk_ddr0_p = ~clk_ddr0_p;
always #3.125 clk_ddr1_p = ~clk_ddr1_p;

assign clk_ddr0_n = ~clk_ddr0_p;
assign clk_ddr1_n = ~clk_ddr1_p;

axi4_mdl #
(
    .NDEV                           (1                          ), 
    .IDW                            (4                          ), 
    .DW                             (128                        ), 
    .DEW                            (16                         ), 
    .AW                             (32                         ), 
    .MAX_BURST_LEN                  (128                        ), 
    .U_DLY                          (U_DLY                      )  // 
)
u_axi4_mdl
(
// ---------------------------------------------------------------------------------
// CLock & Reset
// ---------------------------------------------------------------------------------
    .clk_axi                        (axi4_s0_clk                ), // (input )
    .rst_n                          (rst_sys_n                  ), // (input )
// ---------------------------------------------------------------------------------
// User Data
// ---------------------------------------------------------------------------------
    .axi_wrmem                      (axi_wrmem                  ), // (input )
// ---------------------------------------------------------------------------------
// AXI4
// ---------------------------------------------------------------------------------
    .axi4_awid                      (axi4_s0_awid               ), // (output)
    .axi4_awaddr                    (axi4_s0_awaddr             ), // (output)
    .axi4_awlen                     (axi4_s0_awlen              ), // (output)
    .axi4_awsize                    (axi4_s0_awsize             ), // (output)
    .axi4_awburst                   (axi4_s0_awburst            ), // (output)
    .axi4_awvalid                   (axi4_s0_awvalid            ), // (output)
    .axi4_awready                   (axi4_s0_awready            ), // (input )
                                          
    .axi4_wdata                     (axi4_s0_wdata              ), // (output)
    .axi4_wstrb                     (axi4_s0_wstrb              ), // (output)
    .axi4_wlast                     (axi4_s0_wlast              ), // (output)
    .axi4_wvalid                    (axi4_s0_wvalid             ), // (output)
    .axi4_wready                    (axi4_s0_wready             ), // (input )
                                          
    .axi4_bresp                     (axi4_s0_bresp              ), // (input )
    .axi4_bvalid                    (axi4_s0_bvalid             ), // (input )
    .axi4_bready                    (axi4_s0_bready             ), // (output)
                                          
    .axi4_arid                      (axi4_s0_arid               ), // (output)
    .axi4_araddr                    (axi4_s0_araddr             ), // (output)
    .axi4_arlen                     (axi4_s0_arlen              ), // (output)
    .axi4_arsize                    (axi4_s0_arsize             ), // (output)
    .axi4_arburst                   (axi4_s0_arburst            ), // (output)
    .axi4_arvalid                   (axi4_s0_arvalid            ), // (output)
    .axi4_arready                   (axi4_s0_arready            ), // (input )
                                          
    .axi4_rdata                     (axi4_s0_rdata              ), // (input )
    .axi4_rresp                     (axi4_s0_rresp              ), // (input )
    .axi4_rlast                     (axi4_s0_rlast              ), // (input )
    .axi4_rvalid                    (axi4_s0_rvalid             ), // (input )
    .axi4_rready                    (axi4_s0_rready             )  // (output)
);


sim_examp_axi_ddr4_top #
(
    .U_DLY                          (U_DLY                      )  // 
)
u0_sim_examp_axi_ddr4_top
(
// ---------------------------------------------------------------------------------
// CLock & Reset
// ---------------------------------------------------------------------------------
    .clk_40m                        (clk_40m                    ), // (input )
    .rst_sys_n                      (rst_sys_n                  ), // (input )

    .clk_ddr0_p                     (clk_ddr0_p                 ), // (input )
    .clk_ddr0_n                     (clk_ddr0_n                 ), // (input )
    .clk_ddr1_p                     (clk_ddr1_p                 ), // (input )
    .clk_ddr1_n                     (clk_ddr1_n                 ), // (input )
// ---------------------------------------------------------------------------------
// AXI4
// ---------------------------------------------------------------------------------
    .axi4_s0_clk                    (axi4_s0_clk                ), // (input )
    .axi4_s0_rst_n                  (axi4_s0_rst_n              ), // (input )

    .axi4_s0_awid                   (axi4_s0_awid               ), // (input )
    .axi4_s0_awaddr                 (axi4_s0_awaddr             ), // (input )
    .axi4_s0_awlen                  (axi4_s0_awlen              ), // (input )
    .axi4_s0_awburst                (axi4_s0_awburst            ), // (input )
    .axi4_s0_awsize                 (axi4_s0_awsize             ), // (input )
    .axi4_s0_awready                (axi4_s0_awready            ), // (output)
    .axi4_s0_awvalid                (axi4_s0_awvalid            ), // (input )

    .axi4_s0_wdata                  (axi4_s0_wdata              ), // (input )
    .axi4_s0_wstrb                  (axi4_s0_wstrb              ), // (input )
    .axi4_s0_wlast                  (axi4_s0_wlast              ), // (input )
    .axi4_s0_wready                 (axi4_s0_wready             ), // (output)
    .axi4_s0_wvalid                 (axi4_s0_wvalid             ), // (input )

    .axi4_s0_bid                    (axi4_s0_bid                ), // (output)
    .axi4_s0_bresp                  (axi4_s0_bresp              ), // (output)
    .axi4_s0_bready                 (axi4_s0_bready             ), // (input )
    .axi4_s0_bvalid                 (axi4_s0_bvalid             ), // (output)

    .axi4_s0_arid                   (axi4_s0_arid               ), // (input )
    .axi4_s0_araddr                 (axi4_s0_araddr             ), // (input )
    .axi4_s0_arlen                  (axi4_s0_arlen              ), // (input )
    .axi4_s0_arburst                (axi4_s0_arburst            ), // (input )
    .axi4_s0_arsize                 (axi4_s0_arsize             ), // (input )
    .axi4_s0_arready                (axi4_s0_arready            ), // (output)
    .axi4_s0_arvalid                (axi4_s0_arvalid            ), // (input )

    .axi4_s0_rid                    (axi4_s0_rid                ), // (output)
    .axi4_s0_rdata                  (axi4_s0_rdata              ), // (output)
    .axi4_s0_rresp                  (axi4_s0_rresp              ), // (output)
    .axi4_s0_rlast                  (axi4_s0_rlast              ), // (output)
    .axi4_s0_rready                 (axi4_s0_rready             ), // (input )
    .axi4_s0_rvalid                 (axi4_s0_rvalid             ), // (output)
// ---------------------------------------------------------------------------------
// DDR4 CH0
// ---------------------------------------------------------------------------------
    .ddr4_ch0_addr                  (ddr4_ch0_addr              ), // (output)
    .ddr4_ch0_ba                    (ddr4_ch0_ba                ), // (output)
    .ddr4_ch0_bg                    (ddr4_ch0_bg                ), // (output)
    .ddr4_ch0_cke                   (ddr4_ch0_cke               ), // (output)
    .ddr4_ch0_ck_p                  (ddr4_ch0_ck_p              ), // (output)
    .ddr4_ch0_ck_n                  (ddr4_ch0_ck_n              ), // (output)
    .ddr4_ch0_reset_n               (ddr4_ch0_reset_n           ), // (output)
    .ddr4_ch0_cs_n                  (ddr4_ch0_cs_n              ), // (output)
    .ddr4_ch0_dq                    (ddr4_ch0_dq                ), // (inout )
    .ddr4_ch0_dqs_p                 (ddr4_ch0_dqs_p             ), // (inout )
    .ddr4_ch0_dqs_n                 (ddr4_ch0_dqs_n             ), // (inout )
    .ddr4_ch0_dm_dbi_n              (ddr4_ch0_dm_dbi_n          ), // (inout )
    .ddr4_ch0_odt                   (ddr4_ch0_odt               ), // (output)
    .ddr4_ch0_act_n                 (ddr4_ch0_act_n             ), // (output)
    .ddr4_ch0_ten                   (ddr4_ch0_ten               ), // (output)
    .ddr4_ch0_par                   (ddr4_ch0_par               ), // (output)
// ---------------------------------------------------------------------------------
// DDR4 CH1
// ---------------------------------------------------------------------------------
    .ddr4_ch1_addr                  (ddr4_ch1_addr              ), // (output)
    .ddr4_ch1_ba                    (ddr4_ch1_ba                ), // (output)
    .ddr4_ch1_bg                    (ddr4_ch1_bg                ), // (output)
    .ddr4_ch1_cke                   (ddr4_ch1_cke               ), // (output)
    .ddr4_ch1_ck_p                  (ddr4_ch1_ck_p              ), // (output)
    .ddr4_ch1_ck_n                  (ddr4_ch1_ck_n              ), // (output)
    .ddr4_ch1_reset_n               (ddr4_ch1_reset_n           ), // (output)
    .ddr4_ch1_cs_n                  (ddr4_ch1_cs_n              ), // (output)
    .ddr4_ch1_dq                    (ddr4_ch1_dq                ), // (inout )
    .ddr4_ch1_dqs_p                 (ddr4_ch1_dqs_p             ), // (inout )
    .ddr4_ch1_dqs_n                 (ddr4_ch1_dqs_n             ), // (inout )
    .ddr4_ch1_dm_dbi_n              (ddr4_ch1_dm_dbi_n          ), // (inout )
    .ddr4_ch1_odt                   (ddr4_ch1_odt               ), // (output)
    .ddr4_ch1_act_n                 (ddr4_ch1_act_n             ), // (output)
    .ddr4_ch1_ten                   (ddr4_ch1_ten               ), // (output)
    .ddr4_ch1_par                   (ddr4_ch1_par               )  // (output)
);

generate
for(i=0;i<4;i=i+1) begin:ddr4_loop
ddr4_mdl u0_ddr4_mdl
(
    .ddr4_addr                      (ddr4_ch0_addr              ), // (input )
    .ddr4_ba                        (ddr4_ch0_ba                ), // (input )
    .ddr4_bg                        (ddr4_ch0_bg                ), // (input )
    .ddr4_cke                       (ddr4_ch0_cke               ), // (input )
    .ddr4_ck_p                      (ddr4_ch0_ck_p              ), // (input )
    .ddr4_ck_n                      (ddr4_ch0_ck_n              ), // (input )
    .ddr4_reset_n                   (ddr4_ch0_reset_n           ), // (input )
    .ddr4_cs_n                      (ddr4_ch0_cs_n              ), // (input )
    .ddr4_dq                        (ddr4_ch0_dq[i*16+:16]      ), // (inout )
    .ddr4_dqs_p                     (ddr4_ch0_dqs_p[i*2+:2]     ), // (inout )
    .ddr4_dqs_n                     (ddr4_ch0_dqs_n[i*2+:2]     ), // (inout )
    .ddr4_dm_dbi_n                  (ddr4_ch0_dm_dbi_n[i*2+:2]  ), // (inout )
    .ddr4_odt                       (ddr4_ch0_odt               ), // (input )
    .ddr4_act_n                     (ddr4_ch0_act_n             ), // (input )
    .ddr4_ten                       (ddr4_ch0_ten               ), // (input )
    .ddr4_par                       (ddr4_ch0_par               )  // (input )
);

ddr4_mdl u1_ddr4_mdl
(
    .ddr4_addr                      (ddr4_ch1_addr              ), // (input )
    .ddr4_ba                        (ddr4_ch1_ba                ), // (input )
    .ddr4_bg                        (ddr4_ch1_bg                ), // (input )
    .ddr4_cke                       (ddr4_ch1_cke               ), // (input )
    .ddr4_ck_p                      (ddr4_ch1_ck_p              ), // (input )
    .ddr4_ck_n                      (ddr4_ch1_ck_n              ), // (input )
    .ddr4_reset_n                   (ddr4_ch1_reset_n           ), // (input )
    .ddr4_cs_n                      (ddr4_ch1_cs_n              ), // (input )
    .ddr4_dq                        (ddr4_ch1_dq[i*16+:16]      ), // (inout )
    .ddr4_dqs_p                     (ddr4_ch1_dqs_p[i*2+:2]     ), // (inout )
    .ddr4_dqs_n                     (ddr4_ch1_dqs_n[i*2+:2]     ), // (inout )
    .ddr4_dm_dbi_n                  (ddr4_ch1_dm_dbi_n[i*2+:2]  ), // (inout )
    .ddr4_odt                       (ddr4_ch1_odt               ), // (input )
    .ddr4_act_n                     (ddr4_ch1_act_n             ), // (input )
    .ddr4_ten                       (ddr4_ch1_ten               ), // (input )
    .ddr4_par                       (ddr4_ch1_par               )  // (input )
);
end
endgenerate

endmodule




